FPGA designs
for
reconfigurable converters

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This site offers various designs for reconfigurable FPGA converters. They are all based on Time to Digital Converters. Therefore first an introduction is given into the basic FPGA TDC. It is based on a delay line TDC using the carrychain in the FPGA. For the basic design we will assume a clock synchronous STOP signal and a clock speed > 100 MHz.
This basic FPGA TDC is the basis for both advanced FPGA TDCs and the proposed FPGA ADC. The advanced FPGA TDC can be used for asynchronous START/STOP signals w.r.t. the systems clock or either a slow systems clock.
The designs are based on a basic TDC with a clock conversion speed. E.g. our FPGA ADC runs at 200 MHz and it converts also at 200 MS/s. These were implemented in Xilinx Spartan 6 devices and partially on Artix 7. However they should work, with respectively minor or major changes, on other Xilinx devices or other FPGA brands.

We try to keep an updated overview on papers and other material related to reconfigurable FPGA converters on: FPGA converters in literature. However with the abundance in FPGA TDC papers, the current list only contains a fraction of FPGA TDC publications.

Feel free to contact us for remarks or questions.

Harald Homulle & Edoardo Charbon