Several ways of implementing Time to Digital Converters exists. Especially in ASIC various ways can be easily implemented, such as time counters, oscillators, pulse shrinkers, delay lines and Vernier lines.
For FPGAs on the contrary the design is limited to the FPGA slice structure. Although it is possible to implement reconfigurable versions of TDC oscillators and time counters, they are limited in use due to low resolution or demanding calibration requirements.
As of today the most used structure implemented in a FPGA for TDC purposes is that of the carrychain, i.e. a delay line TDC. The START signal is propagated through a delay line, in ASIC implemented with either buffers or inverters (minimum propagation delay). On the arrival of the STOP signal, the propagated START signal is latched. This directly gives a thermometer time code. The number of stages flipped to one gives the timing information. The resolution of the TDC is given by the buffer or inverter propagation time
A delay line based TDC can be implemented in a FPGA employing the carry structure.
In the FPGA the carrychain is used instead of inverters or buffers, as it is the only structure with a dedicated routing path, i.e. the signal is not routed through the switch boxes, it is the structure with the smallest delay. Furthermore the routing is independent of the compiler making the delay stable with each compile run.
The main limitations are those coming with the FPGA slice structure: the clock domains, clock slew and slack, the carry-look-ahead and the non-uniform delay inter and intra carry slices.
The requirement for the first and most basic TDC is a synchronous STOP signal. E.g. this can be the clock of a pulsed laser or any other reference clock. Ideally the clock should have a high frequency, which can make the delay line short and increase the linearities of the system as the number of clock domain crossings can be reduced.
In the case of a low frequency reference clock or an asynchronous STOP signal, check the page on Advanced FPGA TDC design.
The carry is propagated through the carrychain. In order to achieve a carry that propagates, the sum of the carry should be 1 on the arrival of a carry input of 1. Therefore the carry A and B inputs are respectively 0 and 1. The carry propagates with the speed of the carry elements. This speed is in the order of 15 - 25 ps, dependent on the FPGA platform.
TDC implementation in the FPGA with the carrychain as delay line.
Keeping the carry propagation delay in mind, the length of the delay line can be estimated. The delay line should cover (dependent on the application) the clock period. The line length
where resolution is the carry propagation delay.
E.g. In the case of a 200 MHz clock frequency acting as STOP signal and a resolution of 20 ps, the line length is 250 carries. The line can thus be implemented in 63 slices, each containing a Carry4 primitive.
The first step is the generation of the delay line. This generation can be automated and be placed on the desired location. Manually specifying a starting X, Y location for the delay line ensures best linearity and resolution and the behaviour will be the same each compile run.
The VHDL files can be found below under downloads.
The delay line is generated in
The line has a defined length
The carrychain is placed with the generate statement, while using the
The first block is taken apart as the trigger is the carry input, for the other blocks, the carry in is the carry out of the previous block.
As the blocks are placed as Carry4 entities,
In a similar way, the double flip flops are placed.
In most cases, the compiler will automatically place the flip flops in the desired slices along the Carry4 blocks, in the case it doesn't uncomment the two LOC attributes for the flip flops in the
The resulting thermometer time code has to be converted to binary to be practically usable, the thermometer decoder is in the
Example of a pipelined thermometer to binary decoder with a bit counter in the final stages.
Obviously the bit counter in this small example makes not so much sense. In practice the bit counter is implemented on the last remaining 15 bits, in which the probability of having a bubble is highest.
As the decoder is being pipelined, the latency of a conversion is in the order of 10 clock cycles (dependent on the size of the TDC and therefore the number of pipeline stages required).
Combining this thermometer decoder and the delay line gives a complete and basic synchronous STOP TDC, the accompanying file
In the case of input pulses being longer than the clock period it is useful to shrink them to the end of the clock cycle (especially if the TDC will be shared), also for the sake of getting one conversion value per input pulse. The input filter is implemented as shown in the following figure. It consists of basically two latches that reset itself so as to be able to fire directly after the clock edge.
Input filter with self reset as used to shrink the pulses till the end of the clock cycle and making the encoder only give one output for one input pulse.
The input filter is implemented in the
VHDL files for the basic FPGA TDC.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.