Analog to Digital Converters in FPGAs
Currently the main technique used to implement an ADC in a FPGA is delta sigma modulation. Although a high resolution can be reached, in the order of 10 to 15 bits, the sampling rate is in the order of tens of kHz. As delta sigma modulation depends on a feedback loop it is intrinsically slower than a method without feedback.
A high sampling rate ADC, unreachable with a sigma delta modulator FPGA ADC, therefore requires another technique.
Since 2009 the sampling rate of FPGA TDCs was already in the order of hundreds of MHz. So if the analog signal can be converted to a time domain variable, it can be measured with this high speed TDCs.
Here we show one such technique to make a high speed ADC from a TDC, which we call an Analog through Time to Digital Converter.
From idea to practice
The 200 MS/s ADC (conversion at clock speed) is made converting the analog signal to a time domain variable through a slope comparison scheme. The 200 MHz clock from the FPGA generates a slope to which the analog input is compared. This is implemented using a LVDS input buffer acting as comparator. The time the LVDS generates a 1 at the output is in direct correlation with the analog voltage. Therefore simply measuring this time in a TDC gives a measure for analog voltage. The timing diagram is shown in the following figure.
Timing diagram with IN and OUTPUTs of the ADC.
The system is implemented with two basic TDC as previously described in Basic FPGA TDCs. Additionally required is the LVDS as comparator after which the signal is directly routed to the TDCs input:
The comp_out is connected to one TDC directly and inverted to a second TDC. This way both the rising and falling LVDS signals can measured and time stamped. Both time stamps together form the digital code belonging to the analog input voltage.
Next step is adding the clock manager, which is very specific to the board used and the oscillation frequency of the clock crystal on that board. In this example I will assume a 200 MHz input clock which is used as is and rotated by 180 degrees to generate the output and the STOP signal for TDC 2.
The final toplevel schematic of the VHDL is shown in the figure below. Outside the FPGA the analog input and the resistor of approximately 100 Ω, which is dependent on the required speed and/or analog resolution.
ADC schematic of the top level VHDL with the FPGA IN and OUTPUTs.
VHDL files for the basic FPGA ADC. Some files are shared with the Basic FPGA TDC.
clock_manager_200MHz clock manager for Spartan 6 assuming an input clock of 200 MHz and an output clock of 200 MHz and a clock rotated by 180 degrees;
fine_tdc incorporates the carrychain delay line and the double output buffering;
therm2bin_count is the thermometer decoder with a bit counter in the final stages;
fine_tdc_with_encoder is the bundling of the above;
top the complete implementation of a single ADC channel in which the TDCs and the LVDS buffer are connected;.
GNU GPL License Copyright 2015 Harald Homulle / Edoardo Charbon
This software is released under The GNU General Public License 3. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.