Digital IC Design

Welcome to the course website! This website will be created and updated during the course.

News and Notes.

Please see Blackboard for news and announcements. (Must be logged-in.)
2013-03-28: All slides are available, in 1-up and 6-up version. See below.
2013-03-15: See Project (also link below), updated information about the project.

About the Course

This course will present a broad yet thorough overview of the subject of digital VLSI design, spanning both the circuit and the system abstractions. This complete picture is the only way to make the right tradeoffs, find the most suitable optimizations and the best implementation strategies for very large scale integrated circuits in deep-submicron technologies. After an introduction to technology, devices and interconnect, combinational logic gates and sequential elements are studied. This is followed by system level perspectives of implementation fabrics, interconnect issues, timing issues and the design of macro blocks. At each level, the opportunities and limitations of the physical implementation are considered for finding better solutions and tradeoffs. This includes the consequences of the analog behavior of digital systems with respect to e.g. cross-talk noise and signal waveforms, that generally tend to become more influential with each new technology generation.

The course will include a design project, using Cadence. The grade will be determined for 50% by the exam, and for 50% by the lab course (project) results. In addition, bonus points will be awarded to the teams with the best designs. For a valid overal grade, the partial grades of both the project and the exam both need to be at least a 5.0.

The project will be introduced later.

In addition to the project, there will be two mandatory assignments. These assignments need to be completed, but they will not be graded.

Part 1 of the book (Chapters 1-4) is prerequisite knowledge, although we spent about 1 lecture and a half for review. It will be included in the exam, however. Also, we will later in the course touch upon some of the topics of part 1. Subsequently, we will study from Chapters 5 through 11.

The exam material tentatively is as follows. It is presented as a list of sections to be studied. It might be adapted slightly during the next weeks. Please also study all introductory and conclusion sections of the relevant chapters.

Chapter	Topic	Remarks
Ch 1	Intro	Completely, pay attention to § 1.3
Ch 2	Manufacturing	§ 2.1 - 2.3
Ch 3	Devices	Completely
Ch 4	Interconnect	§ 4.1 - 4.4.4
Ch 5	Inverter	Completely
Ch 6	Combinational	Completely
Ch 7	Sequential	§ 7.1 - 7.5.1
Ch 10	Timing	§ 10.1 - 10.3
Ch 11	Arithmetic	§ 11.1 - 11.3

A written exam will be held on April 18, 2013, from 2 pm to 5 pm.

The exam will be an open-book exam. You are allowed to have the Rabaey book with you. In addition, you may use a printed copy of the lecture slides, possibly with your own annotations. Those annotations should augment the material on the slide, and can't be used for arbitrary information. You are not allowed to consult any other material during the exam.

Practice exams from previous years: 2008, answers (Answer to Question 9c updated 2013-04-16), 2009-a, answers, 2009-b, 2011-a, answers (see note on BB).

Collected exercises from the book: rabaey-exercises-collected.pdf.

Design Project

See Project for more information.

Slides

Here are all the slides of this year's edition of the course.

1up - 6up - Introduction to the course
1up - 6up - Devices (Chapter 3)
1up - 6up - Process (Chapter 2)
1up - 6up - Inverter (Chapter 5)
1up - 6up - Combinational Circuits (Chapter 6)
1up - 6up - Supplement to Combinational, on switching probablity
1up - 6up - Sequential (Clocked Storage) Elements (Chapter 7)
1up - 6up - Timing (Clocking) (Chapter 10)
1up - 6up - Modularity (Chapter 11)
1up - 6up - Interconnect (R, C, Delay) (Chapter 4, not presented)

Extra Material

250nm models and technology data tables from the front/back of (some editions) of the book.

pdf Rabaey Tables

Assignment

Tentative instructions and pointers to be found in Assignment