High-level Electronic (VLSI) System Level Design

Contact: René van Leuken

In this theme, we investigate a trajectory (design flow), that will facilitate a performance conscience methodology to realize digital systems (e.g. SoC's, multi-core, dataflow DSP) starting from high level algorithms. Further, we use this methodology to realize typical complex computing blocks, for example security and safety hardware, multi-core processors, network interconnect, neuron computing, wireless communication blocks or similar complex compute blocks.

The design problem to be solved is how to design, connect and implement large macro IP blocks, in the best possible way, i.e. in terms of speed, bandwidth, power consumption and data reliability. Topics to be covered among others low power optimization and reduction techniques, SoC design methodology, modeling, specification and implementation, communication architecture and protocols.

We work together with a large variety of partners: Medical, Telecom, Security, and technology companies. MSc projects are available in these domains.

Several languages have been developed over the years to support a designer in his design tasks. Most prominent is VHDL and more recently SystemC has emerged. Those languages provide a syntax; how to use such a language in an efficient way is an important research topic. The designer has to make choices between different architectural solutions, different partitions, etc. Typically he is concerned about speed, power, and area. How to find a solution which fulfills his requirements?

Projects under this theme

Computational neuroscience and bio-inspired circuits and algorithms

Low-power neuro-inspired or neuromorphic circuits and algorithms; low-power circuits and systems for neural interfacing.

Resist

Design approach for resilient integrated electronic systems in automotive and avionics applications

Computing Fabric for high performance Applications

Develop an open, flexible and high performance platform by substituting heterogeneous mixed HW/SW specialized sub-systems by application specific processor arrays.