dr.ir. M.R.C.M. Berkelaar

1. Considering Crosstalk Effects in Statistical Timing Analysis
   Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
   IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
   Volume 33, Issue 2, pp. 318-322, February 2014. DOI: 10.1109/TCAD.2013.2279515
   document

2. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
   Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
   IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
   Volume 33, Issue 2, pp. 210-223, February 2014. DOI: 10.1109/TCAD.2013.2287179
   document

3. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Solver
   Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N. van der Meijs;
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
   2013. in press.

4. Considering Crosstalk Effects in Statistical Timing Analysis
   Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
   2013. in press.

5. Direct Statistical Simulation of Timing Properties in Sequential Circuits
   J. Rodriguez; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
   In Proceedings of PATMOS 2012,
   Newcastle upon Tyne, UK, September 2012.
   document

6. Towards An Intrinsically Statistical SPICE-Level Simulator
   M. Berkelaar; Qin Tang; A. Zjajo; J. Rodriguez; N.P. van der Meijs;
   In Proceedings of VARI 2012,
   Sophia Antipolis, France, June 2012.
   document

7. New Statistical Timing Analysis Method Considering Process Variations and Crosstalk
   Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
   In Proceedings of VAMM 2012,
   Dresden, Germany, March 2012.
   document

8. Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations
   Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
   In Proceedings of DATE 2012,
   Dresden, Germany, March 2012.
   document

9. Crosstalk-Aware Statistical Interconnect Delay Calculation
   Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
   In Proceedings of ASPDAC 2012,
   Sydney, Australia, January 2012.
   document

10. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    Volume 58, Issue 1, pp. 164-175, January 2011.
    document

11. Pseudo Circuit Model for Representing Uncertainty in Waveforms
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Design, Automation and Test in Europe (DATE),
    Grenoble, France, March 2011.
    document

12. Voltage Sensitivity Calculation for ViVo-based Gate Models Considering Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In ICT.OPEN,
    Veldhoven, the Netherlands, November 2011.
    document

13. Accuracy Consideration of a Non-Gaussian Interconnect Delay Model for Submicron CMOS Statistical Static Timing Analysis
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International NanoElectronics Conference (INEC),
    Chang Gung University, Tao-Yuan, Taiwan, June 2011.
    document

14. Balanced Truncation of a Stable Non-Minimal Deep-Submicron CMOS Interconnect
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

15. Statistical Delay Calculation with Multiple Input Simultaneous Switching
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

16. Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In Design and Technology of Integrated Systems (DTIS),
    Athens, Greece, April 2011.
    document

17. Statistical Moment Estimation of Delay and Power in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    Journal of Low Power Electronics,
    Volume 6, Issue 4, December 2010. Invited Paper.
    document

18. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    2010. DOI: 10.1109/TCSI.2010.2055291
    document

19. Transistor Level Waveform Evaluation for Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010. 6 pages.
    document

20. RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In IEEE Design Automation Conference (DAC),
    Anaheim, California, pp. 787-792, June 2010.
    document

21. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS),
    Grenoble, France, September 2010.
    document

22. Statistical Moment Estimation in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010.
    document

23. Noise Analysis of Non-Linear Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE Custom Integrated Circuits Conference (CICC 2010),
    San Jose, California, September 2010.
    document

24. Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010),
    Shanghai, China, November 2010.
    document

25. A Simplified Transistor Model for CMOS Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2009. ISBN 978-90-73461-62-8.
    document

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